This invention relates to data processing circuitry for use in the arithmetic and logic sections of digital computers and digital data processors. This invention is particularly useful in providing a novel storage protection system for a data processor and hence will be described primarily in that context.
As is known, it is frequently desirable to restrict access to various storage areas in the data storage system associated with a digital data processor to particular authorized users. This is done primarily for data security and data integrity reasons. In particular, in a large scale data storage system, a certain storage area may be assigned to a particular user or customer and it is desirable to prevent other users or customers from gaining access to or disturbing the data in such storage area. In other words, it is often desirable to protect certain storage areas so as to prevent the use of the data stored therein by unauthorized persons.
Various storage protection systems have been heretofore proposed. One such system makes use of storage protection keys or codes which are used to protect known fixed size storage areas. In order to gain access to a particular one of these fixed size storage areas, the user must initially enter the proper protection key or protection code. Such a system performs quite satisfactorily but suffers from the disadvantage that is limited to use with storage areas of predetermined fixed size. In a goodly number of cases, it would be desirable to instead protect storage areas of various different sizes and to be able to change the sizes and locations of the protected areas from time to time.
Another previously proposed form of storage protection involves the use of upper and lower boundary limits which can be assigned to a particular storage area of a desired selectable size. To initially gain access to the protected storage area, the user must submit the proper identification code. Thereafter, a mechanism within the data processor is used to examine subsequently submitted storage address requests to ensure that they lie within the range set by the upper and lower address limit boundaries. If the user attempts to go beyond either of these boundaries, the data processor stops processing his requests and gives him an out-of-bounds signal. Such boundary limit systems provide the flexibility lacking in the protection key systems. The previously proposed boundary limit type systems, however, have substantial room for improvement in terms of the time required to perform the storage address checking function.
The present invention provides a unique combination of data processing circuitry which can be used to significantly reduce the time required of the data processor for performing the storage address checking function in a boundary limit type storage protection system. This is accomplished by providing data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle. With this circuitry, the upper boundary address checking function is performed in parallel with and during the same machine cycle used for the accessing of the data into or out of the storage system.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.